1.Field of the Invention
This invention relates to the fabrication of heat sinks for high power semiconductor devices and to the integration of the devices with planar microstrip circuitry.
2.Description of the Related Art
High power semiconductor devices such as Gunn diodes, heterojunction bipolar transistors (HBTs), p-channel high electron mobility transistors (p-HEMTs) and field effect transistors (FETs) generate a lot of heat during operation that must be removed to maintain the device's performance and prevent damage. The standard approach is to provide a passive heat sink that draws heat away from the device and dissipates it in the ambient environment. The preferred heat sink and method of fabrication would be easy to manufacture, low cost, and highly integratable, provide adequate thermal transfer performance, and enable reliable electrical connections without degrading the device's electrical performance. To achieve these goals, the heat sink must be very close to the device's active layers, the wafer should not require dicing to form the discrete devices, the discrete devices should not be individually packaged, and the device should be mounted in such a manner that planar electrical connections can be used.
Crowley et al., "140 Ghz indium phosphide Gunn diode" Electronics Letters, Mar. 17, 1994, vol. 30, No. 6, pp. 499-500 discloses a method of fabricating and packaging a Gunn diode with an integral heat sink. As shown in FIG. 1 of Crowley et al, buffer and active layers are grown on an InP substrate. The wafer is thinned and metallised on both sides to form a top metal contact on the thinned substrate and an integral heat sink on the active layer. A FeCl.sub.2 light sensitive etchant is used to define and release the discrete devices without dicing. The formation of the heat sink directly on the diode's active layers generally improves heat transfer. However, the parasitic series resistance associated with the substrate and buffer layer tends to degrade the electrical performance of the diode.
As shown in FIG. 2 of Crowley et al., non-planar assemblies use discrete Gunn diodes, which are compression bonded to individual threaded copper studs. A quartz ring is formed around the Gunn diode and gold ribbons in the shape of a cross are compression bonded to the top contact of the Gunn diode and the quartz ring. A copper lid is used to form a hermetic enclosure for the diode and extend the top contact. The individual packaged Gunn diodes are screwed into a circuit board or block and the elevated top contact is wire bonded to the circuitry on the board. Furthermore, if the Gunn diode should fail, a technician must unscrew and replace the stud. Discrete packaging is expensive and limits integration.
K. Okaniwa et al., "A Novel FET Structure of Buried Plated Heat Sink for Superior High Performance GaAs MMICs" IEEE GaAs IC Symposium, 1990, pp. 233-236 discloses a method of fabricating a parallel FET structure that is connected to a buried heat sink to improve output power and efficiency. As shown in FIGS. 1 and 2a-2e of K. Okaniwa et al, FET electrodes are formed on the frontside of a wafer using conventional processing. Thereafter, via holes from the FET sources are etched down to a depth of 30 microns, the wafer is thinned and chemically etched to form a single tub that exposes the bottoms of multiple via holes. The tub is filled with a plated gold metal to a) short all the source electrodes so that the FETs are connected in parallel to form a single power FET and b) to provide a heat sink. This process is highly integrated, in fact the power FET is directly integrated with other circuitry on the wafer. The process does not require dicing and facilitates planar connections to the other circuitry. However, this process does not produce discrete devices with integrated heat sinks, and further the 30 micron substrate reduces thermal transfer efficiency and increases conduction loss of the microstrip.
J. S. Kofol et al., "A Backside Via Process for Thermal Resistance Improvement Demonstrated Using GaAs HBTs", IEEE GaAs IC Symposium, pp. 267-270, 1992 discloses a method for reducing the operating temperature of HBTs while maintaining the compact device layout needed for high frequency operation. The top side of the wafer is processed to form the HBTs. The conventional process is modified in two ways to accommodate the backside thermal via (BTV) process. First, additional epitaxial layers are formed underneath the usual HBT layers to 1) provide selective etch stopping during backside etching, 2) separate topside circuit elements from BTV metal for AC isolation and 3) DC isolate buried subcollector layers from BTV ground. Second, a via hole is etched to provide an optional through-chip ground. The backside of the wafer is thinned to 100 microns and then etched leaving a 5 micron membrane of wafer material beneath the HBT. The tub is plated with gold to form the heat sink.
Although Kofol's heat sink is "close" to the HBT, the process has several drawbacks. First the additional epitaxial layers increase the parasitic series resistance, which degrades the HBT's performance. Second, the wafer must be diced to release the individual devices. This is time consuming, expensive, and may damage the HBTS. Lastly, the device cannot be grabbed topside because of the circuitry. As a result, the HBT's heat sink cannot be compression bonded but must be epoxy bonded when it is mounted on a circuit board, which reduces heat dissipation.